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FPGA/SoC Board Bring-Up - DDR3 (Zynq Part 2) - Phil's Lab #97

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How to configure and test DDR3 memory on custom Zynq-based hardware. Showing hardware set-up, fly-by routing strategy, Vivado and Vitis configuration, as well as memory area and eye diagram tests. [SUPPORT] Free trial of Altium Designer: Patreon: Mixed-signal hardware design course: Advanced Hardware Design Course Survey: [GIT] [LINKS] Instagram: Zynq-7000 series: Vivado/Vitis: Previous video: TI eye diagram video: W2AEW eye pattern video: [TIMESTAMPS] 00:00 Introduction 01:40 Previous Video 01:56 Altium Designer Free Trial 02:25 DDR3 Hardware Design Overview 06:19 Vivado DDR3 Configuration (Datasheet) 13:15 Vivado Training/Board Details (PCB Delays) 17:46 Export Hardware (XSA) 18:24 Vitis DRAM Test Set-Up 19:52 Hardware Connection 20:08 Memory Address Space Test 22:26 Eye Diagram Tests 24:29 Summary & What’s Next 25:22 Outro

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