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The lighting fast speeds of double-data-rate 5 (DDR5) data, require many signal integrity (SI) engineers to invest significant analysis time, ensuring that data signals will meet the bit-error rate (BER) and mask requirements associated with the Joint Electron Device Engineering Council (JEDEC) data bus specification. This talk from Jayaprakash Balachandran, technical lead at Cisco, shows that while the data bus gets all the glory, there are other parts of DDR design and analysis that also deserve attention. See how Cisco engineers spent part of their DDR analysis time and uncovered a problem before the prototype stage, thereby avoiding a costly re-spin of a PCB. Connect with Cadence: Website: YouTube: Facebook: LinkedIn: Twitter: About Cadence: Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design™ strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence® customers are the world’s most innovative companies, delivering extraordinary products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at .
