The RISC-V Instruction Tier List

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13 Aug 2025

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00:00 - Intro 01:56 - 32-bit base instructions 02:08 - LUI 03:54 - AUIPC 07:14 - JAL 09:09 - JALR 09:56 - BEQ, BNE, BLT, BGE, BLTU, BGEU 11:24 - LB, LH, LW, LBU, LHU, SB, SH, SW 12:46 - ADDI 13:52 - SLTI, SLTIU 14:43 - XORI 15:26 - ORI, ANDI 15:43 - SLLI, SRLI, SRAI 16:10 - ADD, SUB 16:47 - SLL 17:11 - SLT, SLTU 17:22 - XOR 17:37 - SRL, SRA 17:42 - OR, AND 17:49 - FENCE, 21:15 - ECALL 22:41 - EBREAK 23:21 - 64-bit base instructions 23:34 - LWU, LD, SD 24:02 - ADDIW, SLLIW, SRLIW, SRAIW, ADDW, SUBW, SLLW, SRLW, SRAW 24:40 - PAUSE (Zihintpause) 25:58 - FENCE.I (Zifencei) 26:46 - , (Zicond) 28:01 - CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI (Zicsr) 29:18 - M extension 29:48 - MUL, MULH, MULHSU, MULHU 30:49 - DIV, DIVU, REM, REMU 31:29 - MULW, DIVW, DIVUW, REMW, REMUW 31:44 - A extension 31:56 - LR, SC 33:44 - AMOSWAP, AMOADD, AMOXOR, AMOAND, AMOOR 34:25 - AMOMIN, AMOMAX, AMOMINU, AMOMAXU 34:45 - F, D extensions 35:15 - FLW, FSW, FLD, FSD 35:32 - FADD, FSUB, FMUL, FDIV, FMIN, FMAX 36:09 - FMADD, FMSUB, FNMADD, FNMSUB 37:03 - FSQRT 37:18 - FSGNJ, FSGNJN, FSGNJX 37:55 - FEQ, FLT, FLE 38:15 - FCLASS 38:46 - FCVT 39:12 - FMV 40:26 - Finale 41:09 - Outro Source:

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