EEVblog #1247 - DDR Memory PCB Propagation Delay & Layout

When does PCB propagation delay matter in PCB layout? Dave goes down the rabbit hole from DIY TTL processor design to DDR memory design and layout. DDR memory termination. What is a timing budget? When is it important? How does signal integrity matter? When do you have to do serpentine PCB traces to match trace and differential pair lengths? Micron DDR memory timing budget design: The CIAA Project How to lay out a PCB: Forum: #PCB #Layout #DDRmemory Bitcoin Donations: 38y7DE8HEHNj8fGDtUr4PkCn9nWxiorvvy Litecoin: ML7oQokTwB38bgzzjLDbRV97HKAHuwRfHA Ethereum: 0x11AceA38DCA9DbFfB4F35f3F746af65F9dED28ce EEVblog Main Web Site: The 2nd EEVblog Channel: Support the EEVblog through Patreon! AliExpress Affiliate: Buy anything through that link and Dave gets a commission at no cost to you. Stuff I recommend: Donate With Bitcoin & Other Crypto Currencies! T-Shirts: Likecoin – Coins for Likes: @eevblog/dil9/hcq3 Теги: eevblog,video,ddr memory,ddr3,ddr4,ddr timing budget,timing budget,pcb layout,pcb design,serpentine,trace length,tutorial,high speed design,signal integrity,ddr termination,rogers pcb,fr4 pcb,pcb material,signal propogation,double data rate