Guest
Lisa Su, Chair and Chief Executive Officer, AMD, Austin, TX Although traditional scaling has slowed over the past decade, we have made tremendous progress as an industry with new approaches including chiplet-based architectures, domain-specific accelerators, and advanced packaging technologies which have enabled major milestones including the first exascale supercomputers. As we look into the future, we need to accelerate the pace of innovation to drive the next decade of advancement in high-performance computing. By far, the largest limiting factor to delivering continued compounded growth in computation power is energy efficiency. This paper highlights a holistic strategy for accelerating innovation in energy efficiency required for next-generation high-performance computing and ultimately achieving zetta-scale performance. These approaches will be built on continued innovation in process technologies, modular chiplet architectures, and advanced packaging. Fully meeting the challenge will require new dimensions of improvement through extending domain-specific architectures to accelerate core algorithms in combination with the wide-scale deployment of AI across all aspects of the system from transistors to software.
