How to make via-hole on existing PCB design less capacitive with Simbeor software

PCB via-holes can easily destroy the signal, if not properly designed for a particular signaling standard. Well designed via must be localized at least up to the Nyquist frequency and have sufficiently low reflection over a bandwidth of the signal spectrum. The via design should be done in advance, ideally, during the stackup planning step. But, what if it is not done and some vias on the final PCB are reflective or have wrong “impedance“. Both via localization frequency and effective impedance can be quickly evaluated with the model-based ERC in Simbeor as demonstrated in this short video. The effective impedance is just a preliminary measure and, to make via-hole less reflective, 3D EM analysis should be be used after that, to tune or optimize via as demonstrated in this video as whole process takes 5-10 min with the analysis running on just one computer (can be further accelerated with parallelization locally or on AWS). CMP-28 validation platform from Wild River Technology is used - this via is made intentionally capacitive for the analysis to measurement validation purpose. See more on the localization of vias in other videos at Simbeor channel @simbeor/videos or in Simbeor app notes at