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1. Aim : To design the BCD to Seven Segment Decoder PAL circuit, verifying its truth table and hardware of the same on zero PCB. 2. Objectives : i. To design BCD to Seven Segment Decoder circuit using PAL. ii. Basic two or multiple inputs AND, OR, and NOT gates using BC547 NPN transistor and 1k resistors. iii. Hardware circuit of the PAL on zero PCB. iv. To verify the truth table of the BCD to Seven Segment Decoder on hardware. 3. What is Programmable Array Logic: A most commonly used type of Programmable Logic Device i.e. PLD is programmable array logic (PAL). It is a programmable array of logic gates on a single chip in AND-OR configuration. It has a programmable AND array and a fixed OR array in which each OR gate gets inputs from some of the AND gates, i.e. all the AND gate outputs are not connected to any OR gate. 4. Seven segment display pinouts: There are two types of Seven Segment displays the common anode type and the common cathode type. Here in the project, a common cathode type is used. We know this type of display requires a 5V VCC signal for each segment i.e. a, b, c, d, e, f, and g. And the cathode of each LED is common and is connected to the ground. 5. Truth Table Verification: Truth table consisting of total of 16 decimal digits with their four-bit BCD codes and corresponding seven-segment display outputs.
